Avrum's Clock Domain Crossing Widsom

Posted on Mon 22 August 2016 in Hardware • Tagged with VHDL, Vivado

Avrum is an active fellow on the Xilinx forums whenever clock domain crossing (CDC) issues crop up. By default, and in contrast to ISE, Vivado assumes all clocks are related. Thus, even with a proper synchronization circuit, Vivado needs to be explicitly told not to try and time these paths ...

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