Avrum's Clock Domain Crossing Widsom

Avrum is an active fellow on the Xilinx forums whenever clock domain crossing (CDC) issues crop up. By default, and in contrast to ISE, Vivado assumes all clocks are related. Thus, even with a proper synchronization circuit, Vivado needs to be explicitly told not to try and time these paths. Avrum does an excellent job of explaining the correct constraint relaxation to use and why not use what I call the “ostrich method” of just setting the clocks as asynchronous using set_clock_groups -asynchronous or set_false_path between all path between the clocks. This certainly is the easy way out but means you’ll clobber all other more delicate constraints and could mask a real clock crossing problem where you’ve forgotten to synchronize. I’ve tried to collect his posts here for reference: